The present invention is directed generally to digital video signal processing, and more particularly, to integrated decode systems, methods and articles of manufacture which allow selective scaling of video presentation by a predetermined reduction factor, while at the same time allowing for reduced external memory requirements for frame buffer storage. The disclosed MPEG decoder also includes logic for displaying scaled video in a flicker-free fashion.
The MPEG-2 standard describes an encoding method that results in substantial bandwidth reduction by a subjective lossy compression followed by a lossless compression. The encoded, compressed digital data is subsequently decompressed and decoded in an MPEG-2 compliant decoder. Video decoding in accordance with the MPEG-2 standard is described in detail in commonly assigned United States Letters Patent No. 5,576,765, entitled xe2x80x9cVideo Decoderxe2x80x9d, which is hereby incorporated herein by reference in its entirety.
Video decoders are typically embodied as general or special purpose processors and memory. For a conventional MPEG-2 decoder, two decoded reference frames are typically stored in memory at the same time. Thus, the cost of memory can often dominate the cost of the decode system. For example, an MPEG-2 video decoder might employ 2 MB or more of external memory, which generally comprises Dynamic Random Access Memory (DRAM). External memory is used for various data areas, or buffers such as frame buffers.
In practice, the MPEG-2 video decoder is typically limited to 2 MB of external memory in order to minimize cost of the end product. The decoder must perform all of its functions within this limitation. For example, of particular importance is enabling output for both the European market which utilizes the PAL standard of 576 video scan lines and the U.S. market which utilizes the NTSC standard of 480 video scan lines. Even if there is no 2 MB of external memory limitation, it is advantageous to perform the video decode and display in as small a memory space as possible in order to give the remaining memory to other built-in features, such as on-screen graphics.
The MPEG-2 decompressed video data buffers, also called frame buffers, consume the largest part of external DRAM, therefore they are the prime candidate for memory reduction/compression. The frame buffers contain final pixel display and MPEG-reference data, and hence the reduction technique must also retain high video fidelity.
As the MPEG video decoder market becomes more and more competitive, there is a need for high level of feature integration at the lowest possible cost to achieve success in the marketplace. One such feature that, in the past, would have required circuitry external to the video decoder function is video scaling. The kind of scaling desired is to reduce the size of the display picture by a factor, such as 2 or 4, in both the horizontal and vertical axis.
In view of the above, and in order to establish commercial advantage, a novel design is desired wherein a video scaling feature is built into the video decoder, such that advantageous use of existing decoder hardware can be applied to the processes required to produce a high quality scaled image. In one principal aspect, the present invention addresses this need.
Briefly summarized, this invention comprises in one aspect a video decoding system which includes a video decoder for decoding an encoded stream of video data and a decimation unit coupled to the video decoder. The video decoder produces a decoded stream of video data and the decimation unit is adapted to scale the decoded stream of video data for display. The system further includes anti-flicker logic for reducing flicker between adjacent pixels of a display of a frame of the decoded stream of video data. The flicker results from the decimation unit""s scaling of the decoded stream of video data for display.
In another aspect, the invention comprises video display logic for a digital video decoding system. The video display logic includes upsample logic for placing a decoded stream of video data in interlaced format, and anti-flicker logic associated with the upsample logic for reducing flicker between adjacent pixels of a display of a frame of the decoded stream of video data. The flicker comprises visually perceptible frequency change between adjacent pixels of the display of the frame in interlaced format.
In yet another aspect, the invention comprises a method for processing an encoded stream of video data for display. The method includes: decoding the encoded stream of video data to produce a decoded stream of video data; scaling the decoded stream of video data to downsize the decoded stream of video data and provide a downsized decoded stream of video data for display; and reducing a flicker. between adjacent pixels of a display of a frame of the downsized decoded stream of video data, wherein the flicker comprises visually perceptible frequency change between adjacent pixels resulting from the scaling of the decoded stream of video data for display.
In yet another aspect, a method for processing a decoded stream of video data for display is provided. This method includes: upsampling the decoded stream of video data to place the decoded stream of video data in interlaced format; and reducing flicker between adjacent pixels of a display of a frame of the decoded stream of video data, wherein the flicker comprises visually perceptible frequency change between adjacent pixels of the display of the frame in interlaced format.
In a further aspect, an article of manufacture is provided which includes a computer program product comprising computer usable medium having computer readable program code means therein for use in processing an encoded stream of video data for display. The computer readable program code means in the computer program product includes: computer readable program code means for causing a computer to effect decoding the encoded stream of video data to produce a decoded stream of video data; computer readable program code means for causing a computer to effect scaling the decoded stream of video data to downsize the decoded stream of video data and provide a downsized decoded stream of video data for display; and computer readable program code means for causing a computer to effect reducing flicker between adjacent pixels of a display of a frame of the downsized decoded stream of video data, wherein the flicker comprises visually perceptible frequency change between adjacent pixels resulting from the scaling of the decoded stream of video data for display.
In a still further aspect, an article of manufacture is provided which comprises a computer program product having a computer usable medium with computer readable program code means therein for use in processing a decoded stream of video data for display. The computer readable program code means in the computer program product includes: computer readable program code means for causing a computer to effect upsampling of the decoded stream of video data to place the decoded stream of video data in interlaced format; and computer readable program code means for causing a computer to effect reducing flicker between adjacent pixels of a display of a frame of the decoded stream of video data, wherein the flicker comprises visually perceptible frequency change between the adjacent pixels of the display of the frame in interlaced format.
To restate, disclosed herein is a digital video decode system, method and article of manufacture which present an integrated scaling capability. The decoder is arranged such that it reduces the overall bandwidth to external memory when in the scaling mode. For example, the display picture can be reduced by a factor of 2 and/or 4 in both the horizontal and vertical axis. Advantageously, the integrated scaling function for the video decode system presented herein uses existing decoder hardware to produce a high quality scaled image.
By performing decimation/scaling at decode time, the total memory bandwidth requirement is reduced, making more memory bandwidth available to other features, such as on-screen graphics. Thus, scaling implemented in accordance with this invention requires less external memory (i.e., frame buffer memory) than would be required by a post-processing approach, i.e., a display scaler would require four full size frame buffers. Further, in accordance with this invention, switching between non-scaling and scaling modes does not produce display artifacts. Scaling in accordance with this invention can also be employed with B frame memory reduction in full frame format, as well as with letterbox format.
The digital video decode system, method and article of manufacture presented herein further include anti-flicker logic for displaying video, particularly scaled video, in a flicker-free fashion. The anti-flicker logic is implemented without significant additional hardware by utilizing existing upsample hardware within the system""s video display unit.